1. Field of the Invention
This invention relates to a liquid crystal display, and more particularly, to a driving circuit built-in liquid crystal display panel and a fabricating method thereof.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) used as a display device, for example, in a television, a desktop monitor, a personal digital assistant (PDA) or a portable computer, controls light transmittance of liquid crystal using an electric field, thereby displaying a picture. To this end, the LCD includes a liquid crystal display panel having liquid crystal cells arranged in a matrix type and a driving circuit for driving the liquid crystal display panel.
As shown in FIG. 1, a related art LCD includes a liquid crystal display panel 13 having m×n liquid crystal cells Clc arranged in a matrix, m data lines D1 to Dm and n gate lines G1 to Gn intersecting each other, and thin film transistors TFT provided at intersections thereof. The LCD also includes a data driving circuit 11 for applying data signals to the data lines D1 to Dm of the liquid crystal display panel 13 and a gate driving circuit 12 for applying a scanning pulse to the gate lines G1 to Gn.
The liquid crystal display panel 13 is formed by joining a thin film transistor substrate provided with a thin film transistor array to a color filter substrate provided with a color filter array with a liquid crystal layer therebetween. The data lines D1 to Dm and the gate lines G1 to Gn provided at the thin film transistor substrate of the liquid crystal display panel 13 cross each other perpendicularly. The thin film transistor TFT provided at each intersection between the data lines D1 to Dm and the gate lines G1 to Gn applies a data voltage supplied via the corresponding data line to a pixel electrode of the liquid crystal cell Clc in response to a scanning pulse from the corresponding gate line. The color filter substrate is provided with such elements as a black matrix, a color filter, a common electrode, etc. The liquid crystal cell Clc rotates liquid crystal molecules having a dielectric anisotropy by a potential difference between a data voltage supplied to the pixel electrode and a common voltage supplied to the common electrode to thereby control light transmittance. A polarizer having a perpendicular light axis is attached onto the thin film transistor substrate and the color filter substrate of the liquid crystal display panel 13, and an alignment film for determining a free-tilt angle of the liquid crystal is further provided on the inner surface coming in touch with the liquid crystal layer. Further, each liquid crystal cell Clc is provided with a storage capacitor Cst. The storage capacitor Cst is provided between the pixel electrode and the pre-stage gate line or between the pixel electrode and a common line (not shown), thereby maintaining a data voltage charged in the liquid crystal cell Clc constant.
The data driving circuit 11 converts an input digital video data into an analog data voltage using a gamma voltage and applies the converted analog data voltage to the data lines D1 to Dm. The gate driving circuit 12 sequentially applies a scanning pulse to the gate lines G1 to Gn to thereby select a horizontal line of the liquid crystal cell Clc to be supplied with the data.
Such an LCD forms a thin film transistor TFT from a polycrystalline silicon or an amorphous silicon. The polycrystalline silicon has a relatively high charge mobility such that a driving circuit requiring a fast response speed can be built in the liquid crystal display panel. Recently, there has been highlighted a scheme in which the driving circuit can be built in the liquid crystal display panel even when an amorphous silicon is used.
As shown in FIG. 2, a gate driving circuit 20 having a relatively simple circuit configuration is built in a liquid crystal display panel 30 employing an amorphous silicon. The gate driving circuit 20 includes a shift register for sequentially applying a scanning pulse to the gate lines G1 to Gn of the display area 10. The shift register comprises 1st to n-th stages connected in a cascade as shown in FIG. 3. The first to n-th stages are commonly supplied with a clock signal CLK, along with a high-level driving voltage (not shown), and with a start pulse Vst or an output signal of the previous stage. The first stage outputs a scanning pulse to the first gate line GL1 in response to the start pulse Vst and the clock signal CLK. Further, the second to n-th stages sequentially outputs a scanning pulse to the second to n-th gate lines G2 to Gn, respectively, in response to an output signal of the previous stage and the clock signal CLK. At least two clock signals having different phases are used for the clock signal CLK.
A circuit area having the gate driving circuit 20 built in and a line on glass (LOG) area provided with a clock line CLKL for applying the clock signal CLK to the gate driving circuit 20 are located outside the display area 10, that is, in a non-display area. Thus, the circuit area and the LOG area overlap with a black matrix 32 provided at the non-display area of the color filter substrate.
However, as the black matrix 32 is formed from a metal such as chrome (Cr), a parasitic capacitance C is provided between the black matrix 32 and the clock line CLKL. Thus, the parasitic capacitance C of the clock line CLK, along with a line resistance R of the clock line CLKL, distorts the clock signal CLK and the scanning pulse from the gate driving circuit 20. As can be seen from FIG. 4, a scanning pulse applied to the nth gate line Gn is distorted due to the parasitic capacitance R and line resistance R of the clock line CLKL such that a rising time and a falling time of the scanning pulse are similar to a width (approximately 14 μs) of the clock signal CLK.